1. Field of the Invention
The present invention relates to a memory system which is available for a small-sized information terminal such as a cellular phone.
2. Related Art
A memory system of a small-sized information terminal such as a cellular phone mainly includes a linear flash memory for storing CPU command codes and various data, and an SRAM for storing data temporarily as a work area of the CPU. Especially in a small-sized information terminal such as a cellular phone which is strictly limited in the mounting area, the linear flash memory and SRAM are contained in one package, which is known as a multi-chip package (MCP).
In the recent trend for higher function of terminals and higher speed of communications, a larger memory capacity has been strongly demanded, and the capacity shortage of the linear flash memory and SRAM has posed a problem.
To solve such problems, as for the SRAM, it is possible to increase the memory capacity by employing a pseudo-SRAM element which uses a dynamic memory cell of one-transistor type same as in the DRAM and has the same interface as that of the SRAM.
On the other hand, regarding the storage flash memory, the AND/NAND storage flash memories of block (sector) access type suited to application of large capacity storage are manufactured. However they cannot be easily coupled directly to the CPU bus owing to their characteristic in the specification. Therefore there are problems in which a dedicated interface circuit must be fitted externally or only low speed access is achieved by port connection with the CPU. Besides, since direct random access to the storage flash memory is impossible, in order to achieve a random access function, the data has to be transferred once onto the RAM and then the CPU has to access the RAM. This method requires a large capacity of RAM.
To solve such defects specific to the storage flange memory, the pseudo-SRAM element has been developed which incorporates the interface circuit or control functions of the storage flash memory (refer to Japanese Patent Application No. 2001-111259). It hence solves the problem of mismatching of the storage flash memory and CPU interface, and the memory capacity can be increased.
However, the following defects exist in data transfer in the MCP having such a pseudo-SRAM element. When an access from the external CPU occurs during data transfer between the storage flash memory and the pseudo-SRAM element, conflict occurs between transfer requests. It becomes a problem that how this conflict is arbitrated.